Sdio Data Fifo Register (Sdio_Fifo); Sdio Register Map; Table 132. Sdio Register Map - ST STM32F102 Series Reference Manual

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SDIO interface (SDIO)

SDIO Data FIFO Register (SDIO_FIFO)

Address offset: 0x80

Reset value: 0x0000 0000

The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs

contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store

multiple operands to read from/write to the FIFO.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

bits 31:0 FIFOData: Receive and transmit FIFO data.

The FIFO data occupies 32 entries of 32-bit words, from address:

SDIO base + 0x080 to SDIO base + 0xFC.

The following table summarizes the SDIO registers.

31 30 29 28 27 26 25 24 23 22 21 23 19 18 17 16 15 14 13 12 11 10 9

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