Flexible static memory controller (FSMC)
Mode C - NOR Flash - OE toggling
Figure 166. ModeC read accesses
Figure 167. ModeC write accesses
The differences compared with mode1 are the toggling of NOE and NADV and the
independent read and write timings.
382/690
A[25:0]
NADV
NEx
NOE
NWE
High
D[15:0]
(ADDSET +1)
HCLK cycles
A[25:0]
NADV
NEx
NOE
NWE
D[15:0]
(ADDSET +1)
HCLK cycles
Memory transaction
data driven
by memory
(DATAST + 1)
HCLK cycles
Data sampled
Memory transaction
1HCLK
data driven by FSMC
(DATAST + 1)
HCLK cycles
RM0008
2 HCLK
cycles
Data strobe
ai14725c
ai14723b
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