ST STM32F102 Series Reference Manual page 567

RM0008
master transmission mode, in slave mode, CHSIDE is sensitive to the WS signal coming
from the external master. This means that the slave needs to be ready to transmit the first
data before the clock is generated by the master. WS assertion corresponds to channel Left
transmitted first.
Note: The I2SE has to be written at least two PCLK cycles before the first clock of the master
comes on the CK line.
The data half-word is parallel-loaded into the 16-bit shift register (from the internal bus)
during the first bit transmission, and then shifted out serially to the MOSI/SD pin MSB first.
The TXE flag is set after each transfer from the Tx buffer to the shift register and an interrupt
is generated if the TXEIE bit in the SPI_CR2 register is set.
Note that the TXE flag should be checked to be at 1 before attempting to write the Tx buffer.
For more details about the write operations depending on the I
refer to Section 22.4.2: Supported audio
To secure a continuous audio data transmission, it is mandatory to write the SPI_DR
register with the next data to transmit before the end of the current transmission. An
underrun flag is set and an interrupt may be generated if the data are not written into the
SPI_DR register before the first clock edge of the next data communication. This indicates
to the software that the transferred data are wrong. If the ERRIE bit is set into the SPI_CR2
register, an interrupt is generated when the UDR flag in the SPI_SR register goes high. In
this case, it is mandatory to switch off the I
channel left.
Reception sequence
The operating mode is the same as for the transmission mode except for the point 1. where
the configuration should set the master reception mode using the I2SCFG[1:0] bits in the
SPI_I2SCFGR register.
Whatever the data length or the channel length, the audio data are received by 16-bit
packets. This means that each time the RX buffer is full, the RXNE flag in the SPI_SR
register is set and an interrupt is generated if the RXNEIE bit is set in the SPI_CR2 register.
Depending on the data length and channel length configuration, the audio value received for
a right or left channel may result from one or two receptions into the RX buffer.
The CHSIDE flag is updated each time data are received to be read from SPI_DR. It is
sensitive to the external WS line managed by the external master component.
Clearing the RXNE bit is performed by reading the SPI_DR register.
For more details about the read operations depending the I
to Section 22.4.2: Supported audio
If data are received while the precedent received data have not yet been read, an overrun is
generated and the OVR flag is set. If the bit ERRIE is set in the SPI_CR2 register, an
interrupt is generated to indicate the error.
To switch off the I
the last data reception. Even if I2SE is switched off while the last data is being transferred,
the clock and the transfer go on until the end of the last data transmission.
Note: The external master components should have the capability to send/receive data on 16-bit
or 32-bit packet via an audio channel.
protocols.
2
S in reception mode, I2SE has to be cleared during and before the end of
Serial peripheral interface (SPI)
protocols.
2
S and to restart a data transfer starting from the
2
S standard mode selected, refer
2
S standard mode selected,
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