Figure 136. Gating Timer 2 With Oc1Ref Of Timer 1 - ST STM32F102 Series Reference Manual

RM0008
Using one timer to enable another timer
In this example, we control the enable of Timer 2 with the output compare 1 of Timer 1.
Refer to
OC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the
prescaler compared to CK_INT (f
●
Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIM1_CR2 register).
●
Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).
●
Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR
register).
● Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).
●
Enable Timer 2 by writing '1' in the CEN bit (TIM2_CR1 register).
● Start Timer 1 by writing '1' in the CEN bit (TIM1_CR1 register).
Note: The counter 2 clock is not synchronized with counter 1, this mode only affects the Timer 2
counter enable signal.

Figure 136. Gating timer 2 with OC1REF of timer 1

TIMER1-OC1REF
In the example in
being started. So they start counting from their current value. It is possible to start from a
given value by resetting both timers before starting Timer 1. You can then write any value
you want in the timer counters. The timers can easily be reset by software using the UG bit
in the TIMx_EGR registers.
In the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts
from 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both
Figure 135 for connections. Timer 2 counts on the divided internal clock only when
CK_INT
TIMER1-CNT
FC
TIMER2-CNT
3045
TIMER 2-TIF
Figure 136, the Timer 2 counter and prescaler are not initialized before
= f /3).
CK_CNT CK_INT
FD FE
3046 3047
Write TIF=0
General-purpose timer (TIMx)
FF 00 01
3048
305/690