Smartcard; Figure 250. Iso 7816-3 Asynchronous Protocol - ST STM32F102 Series Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
arbiter, for instance). In particular, the transmission is never blocked by hardware and
continue to occur as soon as a data is written in the data register while the TE bit is set.
24.3.10

Smartcard

The Smartcard mode is selected by setting the SCEN bit in the USART_CR3 register. In
smartcard mode, the following bits must be kept cleared:
●
LINEN bit in the USART_CR2 register,
●
HDSEL and IREN bits in the USART_CR3 register.
Moreover, the CLKEN bit may be set in order to provide a clock to the smartcard.
The Smartcard interface is designed to support asynchronous protocol Smartcards as
defined in the ISO7816-3 standard. USART should be configured as:
●
8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register and either:
–
–
Figure 250
error.

Figure 250. ISO 7816-3 asynchronous protocol

Without Parity error
With Parity error
When connected to a smartcard, the TX output of the USART drives a bidirectional line that
the smartcard also drives into. To do so, SW_RX must be connected on the same I/O than
TX at product level. The Transmitter output enable TX_EN is asserted during the
transmission of the start bit and the data byte, and is deasserted during the stop bit (weak
pull up), so that the receive can drive the line in case of a parity error. If TX_EN is not used,
TX is driven at high level during the stop bit: Thus the receiver can drive the line as long as
TX is configured in open-drain.
Smartcard is a single wire half duplex communication protocol.
● Transmission of data from the transmit shift register is guaranteed to be delayed by a
minimum of 1/2 baud clock. In normal operation a full transmit shift register will start
shifting on the next baud clock edge. In Smartcard mode this transmission is further
delayed by a guaranteed 1/2 baud clock.
● If a parity error is detected during reception of a frame programmed with a 1/2 stop bit
period, the transmit line is pulled low for a baud clock period after the completion of the
receive frame, i.e. at the end of the 1/2 stop bit period. This is to indicate to the
Smartcard that the data transmitted to USART has not been correctly received. This
630/690
0.5 stop bits when receiving: where STOP='01' in the USART_CR2 register
1.5 stop bits when transmitting: where STOP='11' in the USART_CR2 register.
shows examples of what can be seen on the data line with and without parity
2
S 1
0
Start
bit
2
S 1
0
Start
bit
5 6 7
3 4
5
6 7
3 4
Guard time
P
Guard time
P
Line pulled low
by receiver during stop in
case of parity error
RM0008