Channel-By-Channel Programmable Sample Time; Conversion On External Trigger; Figure 26. Right Alignment Of Data; Figure 27. Left Alignment Of Data - ST STM32F102 Series Reference Manual

RM0008

Figure 26. Right alignment of data

Injected group
SEXT
Regular group
0

Figure 27. Left alignment of data

Injected group
SEXT
Regular group
D11
10.6

Channel-by-channel programmable sample time

ADC samples the input voltage for a number of ADC_CLK cycles which can be modified us-
ing the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be
sampled with a different sample time.
The total conversion time is calculated as follows:
Tconv = Sampling time + 12.5 cycles
Example:
With an ADCCLK = 14 MHz and a sampling time of 1.5 cycles:
Tconv = 1.5 + 12.5 = 14 cycles = 1µs
10.7

Conversion on external trigger

Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the EXT-
TRIG control bit is set then external events are able to trigger a conversion. The EXT-
SEL[2:0] and JEXTSEL[2:0] control bits allow the application to select decide which out of 8
possible events can trigger conversion for the regular and injected groups.
Note: When an external trigger is selected for ADC regular or injected conversion, only the rising
edge of the signal can start the conversion.
SEXT SEXT SEXT D11
0 0 0 D11
D11 D10 D9 D8
D10 D9 D8 D7
D10 D9 D8 D7
D10 D9 D8 D7
D7 D6 D5 D4
D6 D5 D4 D3
Analog-to-digital converter (ADC)
D6 D5 D4 D3 D2
D6 D5 D4 D3 D2
D3 D2 D1 D0
D2 D1 D0 0
D1 D0
D1 D0
0 0 0
0 0 0
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