Figure 86. 6-Step Generation, Com Example (Ossr=1) - ST STM32F102 Series Reference Manual

RM0008
Table 174. Document revision history (continued)
Date
08-Feb-2008
22-May-2008
Revision
Figure 4: Power supply overview on page 48
Section 6.1.2: Power reset on page 70
Section 6.2: Clocks on page 70
Definition of Bits 26:24 modified in
configuration register (AFIO_MAPR) on page
bits corrected in
AFIO_EVCR
page 122.
Number of maskable interrupt channels modified in
vectored interrupt controller (NVIC) on page 123
Section 9.3.5: Interrupts on page 138
Examples modified in
(OSSR=1) on page
3
Table 55: Output control bits for complementary OCx and OCxN channels
with break feature on page 263
Register names modified in
page 534.
Small text change in
Bits 5:0 frequency description modified in
(I2C_CR2) on page
Section 20.3.1: Description of USB blocks on page 470
Section 22.3.4: Simplex communication on page 551
Section 22.3.6: CRC calculation on page 552
Note added in
Section 22.3.9: Disabling the SPI on page 555
Appendix A: Important notes, removed.
Reference manual updated to apply to devices containing up to 512 Kbytes
of Flash memory (High-density devices). Document restructured. Small text
changes. Definitions of Medium-density and High-density devices added to
all sections.
In Section 2: Memory and bus architecture on page
– Figure 1: System architecture on page
page 35, Table 1: Register boundary addresses on page 36
– Note and text added to
– SRAM size in
– Section 2.3.4: Embedded Flash memory on page 39
4
page size, number of pages,
continued
module organization (High-density devices) on page 41
on next
– Prefetch buffer on/off specified in
page
bit_number definition modified in
Section 3: CRC calculation unit on page 44
boundary addresses on page 36
page 35 updated and CRCEN bit added to
Clock enable register (RCC_AHBENR) on page
Entering Stop mode on page 54
Updated in Section 5: Backup registers (BKP) on page
backup registers and available storage size and
introduction. ASOE definition modified in
calibration register (BKP_RTCCR) on page
Changes
modified.
Section 7.4.2: AF remap and debug I/O
Table 35: AFIO register map and reset values on
added. Small text changes.
Figure 86: 6-step generation, COM example
236.
modified.
Section 21.6.4: CAN filter registers on
Section 23.3.3: I2C master mode on page
599.
BUSY flag on page 552.
AHB/APB bridges (APB) on page 34
Section 2.3.2: Embedded SRAM on page 38
Reading Flash
Reading Flash memory
Section 2.3.3: Bit banding on page
updated,
specified.
Revision history
modified.
modified.
117.
Section 8.1: Nested
.
Section 23.6.2: Control register 2
modified.
modified.
modified.
added.
33:
33, Figure 2: Memory map on
updated
updated (Flash size,
memory, Table 4: Flash
added)
added (Table 1: Register
Figure 2: Memory map on
Section 6.3.6: AHB Peripheral
87).
61: number of
Section 5.1: BKP
Section 5.4.2: RTC clock
63.
586.
38.
683/690