Rtc Wakeup Timer Register (Rtc_Wutr); Rtc Calibration Register (Rtc_Calibr) - ST STM32F412 Reference Manual

RM0402
Bits 31:23 Reserved, must be kept at reset value
Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor
Bit 15 Reserved, must be kept at reset value.
Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor
Note: This register must be written in initialization mode only. The initialization must be performed
in two separate write accesses. Refer to
This register is write protected. The write access procedure is described in
write protection.
22.6.6

RTC wakeup timer register (RTC_WUTR)

Address offset: 0x14
Backup domain reset value: 0x0000 FFFF
System reset: not affected
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value
Bits 15:0 WUT[15:0]: Wakeup auto-reload value bits
Note: The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting
Note: This register can be written only when WUTWF is set to 1 in RTC_ISR.
This register is write protected. The write access procedure is described in
write protection.
22.6.7

RTC calibration register (RTC_CALIBR)

Address offset: 0x18
Backup domain reset value: 0x0000 0000
System reset: not affected
This is the asynchronous division factor:
ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
This is the synchronous division factor:
ck_spre frequency = ck_apre frequency/(PREDIV_S+1)
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0]
+ 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the
RTC_CR register
When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively
becomes WUT[16] the most-significant bit to be reloaded into the timer.
WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden.
Calendar initialization and configuration
24 23 22
Res. Res. Res.
8 7 6
WUT[15:0]
rw rw rw
RM0402 Rev 6
Real-time clock (RTC)
RTC register
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
RTC register
17 16
Res. Res.
1 0
rw rw
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