ST STM32WL55JC Reference Manual page 358

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Reset and clock control (RCC)
Off-
Register
set
RCC_
AHB1ENR
0x048
Reset value
RCC_
AHB2ENR
0x04C
Reset value
RCC_
AHB3ENR
0x050
Reset value
0x054
Reserved
RCC_
APB1ENR1
0x058
0
Reset value
RCC_
APB1ENR2
0x05C
Reset value
RCC_
APB2ENR
0x060
Reset value
RCC_
APB3ENR
0x064
Reset value
358/1454
Table 63. RCC register map and reset values (continued)
1
0
0 0 0
0 1 0 0 0
Reserved
0
0
0 0
0
RM0453 Rev 2
0
0
0 0
0 0
0 0
0
RM0453
0 0 0
0 0 0
0
0
0

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