Table 99. Crc Register Map And Reset Values - ST STM32WL55JC Reference Manual

Analog-to-digital converter (ADC)
18.2 ADC main features
• High performance
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Low-power
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Analog input channels
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• Start-of-conversion can be initiated:
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Conversion modes
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Interrupt generation at the end of sampling, end of conversion, end of sequence
conversion, and in case of analog watchdog or overrun events
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Analog watchdog
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Oversampler
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ADC supply requirements: 1.62 to 3.6 V
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ADC input range: V
532/1454
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
ADC conversion time: 0.4 µs for 12-bit resolution (2.5Msps), faster conversion
times can be obtained by lowering resolution.
Self-calibration
Programmable sampling time
Data alignment with built-in data coherency
DMA support
The application can reduce PCLK frequency for low-power operation while still
keeping optimum ADC performance. For example, 0.4 µs conversion time is kept,
whatever the PCLK frequency
Wait mode: prevents ADC overrun in applications with low PCLK frequency
Auto off mode: ADC is automatically powered off except during the active
conversion phase. This dramatically reduces the power consumption of the ADC.
12 external analog inputs
1 channel for internal temperature sensor (V
1 channel for internal reference voltage (V
1 channel for monitoring external V
1 channel for monitoring DAC internal channel input
By software
By hardware triggers with configurable polarity (timer events or GPIO input
events)
Can convert a single channel or can scan a sequence of channels.
Single mode converts selected inputs once per trigger
Continuous mode converts selected inputs continuously
Discontinuous mode
16-bit data register
Oversampling ratio adjustable from 2 to 256x
Programmable data shift up to 8-bits
≤ V
SSA
REFINT
power supply pin
BAT
≤ V
IN REF+
RM0453 Rev 2
)
TS
)
RM0453