ST STM32WL55JC Reference Manual page 455

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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RM0453
13.4
DMA functional description
13.4.1
DMA block diagram
The DMA block diagram is shown in
dma1_req [1..7]
dma1_ack [1..7]
dma1_secm [1..7]
dma1_priv[1..7]
dma2_req [1..7]
dma2_ack [1..7]
dma2_secm [1..7]
dma2_priv[1..7]
Figure
49.
Figure 49. DMA block diagram
DMA1
Ch 1
Ch 2
Ch 7
Arbiter
Interrupt
interface
dma1_it[1..7]
DMA2
Ch 1
Ch 2
Ch 7
Arbiter
Interrupt
interface
dma2_it[1..7]
RM0453 Rev 2
Direct memory access controller (DMA)
AHB master interface
AHB slave interface
dma1_ilac
AHB master interface
AHB slave interface
dma2_ilac
MSv61533V1
455/1454
478

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