Figure 255. Complementary Output With Dead-Time Insertion; Figure 256. Dead-Time Waveforms With Delay Greater Than The Negative Pulse - ST STM32WL55JC Reference Manual

General-purpose timers (TIM16/TIM17)
must be inserted (dummy instruction) before reading it correctly. This is because the write
acts on the asynchronous signal whereas the read reflects the synchronous signal.
When a break occurs (selected level on the break input):
•
The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state
or even releasing the control to the GPIO (selected by the OSSI bit). This feature
functions even if the MCU oscillator is off.
• Each output channel is driven with the level programmed in the OISx bit in the
TIMx_CR2 register as soon as MOE=0. If OSSI=0, the timer releases the output control
(taken over by the GPIO) else the enable output remains high.
•
When complementary outputs are used:
–
–
–
•
The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be
generated if the BIE bit in the TIMx_DIER register is set.
• If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again
at the next update event UEV. This can be used to perform a regulation, for instance.
Else, MOE remains low until it is written with 1 again. In this case, it can be used for
security and the break input can be connected to an alarm from power drivers, thermal
sensors or any security components.
Note: The break inputs is acting on level. Thus, the MOE cannot be set while the break input is
active (neither automatically nor by software). In the meantime, the status flag BIF cannot
be cleared.
The break can be generated by the BRK input which has a programmable polarity and an
enable bit BKE in the TIMx_BDTR register.
In addition to the break input and the output management, a write protection has been
implemented inside the break circuit to safeguard the application. It allows the configuration
of several parameters to be freezed (dead-time duration, OCx/OCxN polarities and state
when disabled, OCxM configurations, break enable and polarity). The protection can be
selected among 3 levels with the LOCK bits in the TIMx_BDTR register. Refer to
Section 27.4.14: TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) on
page 935. The LOCK bits can be written only once after an MCU reset.
The Figure 258
914/1454
The outputs are first put in reset state inactive state (depending on the polarity).
This is done asynchronously so that it works even if no clock is provided to the
timer.
If the timer clock is still present, then the dead-time generator is reactivated in
order to drive the outputs with the level programmed in the OISx and OISxN bits
after a dead-time. Even in this case, OCx and OCxN cannot be driven to their
active level together. Note that because of the resynchronization on MOE, the
dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles).
If OSSI=0 then the timer releases the enable outputs (taken over by the GPIO
which forces a Hi-Z state) else the enable outputs remain or become high as soon
as one of the CCxE or CCxNE bits is high.
shows an example of behavior of the outputs in response to a break.
RM0453 Rev 2
RM0453