Proprietary Code Readout Protection (Pcrop) - ST STM32WL55JC Reference Manual

RM0453
WRPx registers values (x = A or B)
WRP1x_STRT = WRP1x_END
WRP1x_STRT > WRP1x_END
WRP1x_STRT < WRP1x_END
Note: To validate the WRP options, the option bytes must be reloaded through the OBL_LAUNCH
bit in FLASH_CR.
4.6.4 CPU2 security (ESE)
All or a part of the Flash memory and SRAM1, SRAM2 memories can be made secure,
exclusively accessible by the CPU2, protected against execution, read and write from third
parties. Only the CPU2 can execute, read and write in these areas, which can only be
reached by the CPU2, while all other accesses (CPU1 and DMA) are strictly prohibited.
CPU2 security is enabled when part or all of the Flash memory is secure (FSD = 0) or when
option byte loading fails. In this case, the ESE bit in FLASH_OPTR is set.
Changing the CPU2 security mode
It is easy to enable the CPU2 security by loading the user opting FSD with 0. Security is
applied in any RDP level.
CPU2 security start address can be modified by the secure CPU2 by loading a new user
option SFSA. To totally disable the security, CPU2 sets the FSD bit. It is a good practice,
prior to removing security from part or all of the memory, to page erase the Flash memory
part that becomes non-secure.
Non-secure CPU1 and secure CPU2 can both remove security by setting the ESE bit to 0 in
FLASH_OPTR and regressing the RDP level from level 1 to level 0. In this case the main
Flash memory, backup registers (RTC_BKPxR in the RTC), SRAM1, SRAM2 and PKA
SRAM are erased as described in
CPU2 secure Flash area
The CPU2 secure Flash area has a 2-Kbyte granularity sector and is defined by the secure
Flash start page offset user option (SFSA) into the Flash memory. This offset is controlled
from the SFSA field in FLASH_SFR.
The CPU2 secure Flash area is defined as:
Flash memory Base address + [SFSA x 0x0800] (included) to the last Flash address.
When CPU2 security is enabled, the minimum CPU2 secure area size is one sector
(2 Kbytes).
For example, with a CPU2 secure area from the address 0x0802 7000 (included) to the
address 0x0803 FFFF (included), FLASH_SFR must be programmed with SFSA = 0x4E.
The ESE flag in FLASH_OPTR indicates if the CPU2 security is enabled.
Any CPU1 access to a CPU2 security area triggers RDERR or WRPERR flag error.
Table 22: WRP protection
Page WRP1x is protected
No WRP, unprotected
Pages from WRP1x_STRT to WRP1x_END are protected
Change the readout protection
RM0453 Rev 2
Embedded Flash memory (FLASH)
WRP protection area
level.
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