Figure 211. External Trigger Input Block - ST STM32WL55JC Reference Manual

General-purpose timer (TIM2)
Input mode
CC1S[1]
CC1S[0]
IC1PS
CC1E
CC1G
TIMx_EGR
TIMx_SMCR
OCREF_CLR
ETRF
ocref_clr_int
CNT > CCR1
CNT = CCR1
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
842/1454
Figure 214. Capture/Compare channel 1 main circuit
APB Bus
MCU-peripheral interface
Capture/compare preload register
Capture
compare shadow register
Figure 215. Output stage of Capture/Compare channel (channel 1)
OCCS
0
1
OC1REF
Output
mode
controller
OC2REF
OC1M[3:0]
OC1CE
TIMx_CCMR1
16/32-bit
Compare
transfer
Comparator
Counter
To the master
mode controller
OC1REFC
'0'
0
Output
1
selector
CC1E
TIMx_CCER
RM0453 Rev 2
Output mode
CC1S[1]
CC1S[0]
OC1PE
UEV
(from time
base unit)
CNT>CCR1
CNT=CCR1
0
Output
enable
1
circuit
CC1P
CC1E TIMx_CCER
TIMx_CCER
RM0453
OC1PE
TIMx_CCMR1
MSv63030V1
OC1
MS33145V5