ST STM32WL55JC Reference Manual page 256

Power control (PWR)
Bits 3:1 PLS[2:0]: Programmable voltage detector level selection.
Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the
Bit 0 PVDE: Programmable voltage detector enable
Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR
6.6.3 PWR control register 3 (PWR_CR3)
This register is not reset when exiting Standby modes.
Access: additional APB cycles are needed to access this register versus those needed for a
standard APB access (three for a write and two for a read).
Address offset: 0x008
Reset value: 0x0000 8000
31 30 29
Res. Res. Res. Res.
15 14 13
EIWUL EC2H Res.
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 EIWUL: internal wakeup line for CPU1 enable
Bit 14 EC2H: CPU2 hold interrupt for CPU1 enable
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These bits select the voltage threshold detected by the programmable voltage detector:
000: V around 2.0 V
PVD0
001: V around 2.2 V
PVD1
010: V around 2.4 V
PVD2
011: V around 2.5 V
PVD3
100: V around 2.6 V
PVD4
101: V around 2.8 V
PVD5
110: V around 2.9 V
PVD6
111: External input analog voltage PVD_IN (compared internally to VREFINT)
SYSCFG_CBR register.
These bits are reset only by a system reset.
0: Programmable voltage detector disabled
1: Programmable voltage detector enabled
register.
This bit is reset only by a system reset.
28 27 26 25
Res. Res. Res.
12 11 10 9
APC RRS
rw rw rw
0: Internal wakeup line interrupt to CPU1 disabled
1: Internal wakeup line interrupt to CPU1 enabled
Enable CPU2 kept in hold, due to C2BOOT, interrupt to CPU1.
0: Interrupt to CPU1 disabled
1: interrupt to CPU1 enabled
24 23 22
Res. Res. Res.
8 7 6
ULPEN Res.
rw rw
RM0453 Rev 2
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res.
rw
RM0453
17 16
Res. Res.
1 0
rw rw