Figure 126. Dma Transfer Of A 128-Bit Data Block During Output Phase - ST STM32WL55JC Reference Manual

AES hardware accelerator (AES)
23.6 AES processing latency
The tables below summarize the latency to process a 128-bit block for each mode of
operation.
Key size
Mode 1: Encryption
128-bit
Mode 2: Key derivation
Mode 3: Decryption
Mode 1: Encryption
256-bit
Mode 2: Key derivation
Mode 3: Decryption
Table 141. Processing latency for GCM and CCM (in clock cycles)
Key size Mode of operation
Mode 1: Encryption/
128-bit
Mode 3: Decryption
Mode 1: Encryption/
256-bit
Mode 3: Decryption
1. Data insertion can include wait states forced by AES on the AHB bus (maximum 3 cycles, typical 1 cycle).
23.7 AES registers
23.7.1 AES control register (AES_CR)
Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. GCMPH[1:0]
rw rw
Bits 31:24 Reserved, must be kept at reset value.
684/1454
Table 140. Processing latency for ECB, CBC and CTR
Mode of operation
Algorithm
GCM
CCM
GCM
CCM
28 27 26 25
Res. Res. Res.
12 11 10 9
ERRIE CCFIE
rw rw rw rw
Init Phase
phase
64
63
88
87
24 23 22
Res. NPBLB[3:0]
rw rw
8 7 6
ERRC CCFC CHMOD[1:0]
rw rw rw
RM0453 Rev 2
Algorithm
ECB, CBC, CTR
-
ECB, CBC, CTR
ECB, CBC, CTR
-
ECB, CBC, CTR
Header Payload
(1) (1)
phase
35 51
55 114
35 75
79 162
21 20 19 18
Res.
rw rw rw
5 4 3 2
MODE[1:0] DATATYPE[1:0]
rw rw rw rw
RM0453
Clock
cycles
51
59
51
75
82
75
(1)
Tag phase
59
58
75
82
17 16
Res.
rw
1 0
EN
rw rw