ST STM32WL55JC Reference Manual page 365

RM0453
8.3 Functional description
8.3.1 HSEM block diagram
As shown in
•
The semaphore block containing the semaphore status and IDs
•
The semaphore interface block providing AHB access to the semaphore via the
HSEM_Rx and HSEM_RLRx registers
•
The interrupt interface block providing control for the interrupts via the HSEM_CnISR,
HSEM_CnIER, HSEM_CnMISR, and HSEM_CnICR registers.
hclk
8.3.2 HSEM internal signals
Signal name
BusMasterID
hsem_intn_it
8.3.3 HSEM lock procedures
There are two lock procedures, namely 2-step (write) lock and 1-step (read) lock. The two
procedures (1-step and 2-step) can be used concurrently.
Figure 33, the HSEM is based on three sub-blocks:
Figure 33. HSEM block diagram
HSEM
Bus master ID
Semaphore block
Semaphore 0
Semaphore 1
Semaphore x
Table 64. HSEM internal input/output signals
AHB bus Digital input/output
Semaphore interface
2
Sem_Ints
HSEM_R0
HSEM_RLR0
2
Sem_Ints
HSEM_R1
HSEM_RLR1
2
Sem_Ints
HSEM_Rx
HSEM_RLRx
Signal type
AHB register access bus
Digital input AHB bus master ID
Digital output Interrupt n line (n = 1 to 2)
RM0453 Rev 2
Hardware semaphore (HSEM)
Interrupt interface
HSEM_CnICR[1:0]
Description
hsem_int1_it
hsem_int2_it
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