Figure 43. Basic Structure Of A Standard I/O Port Bit - ST STM32WL55JC Reference Manual

General-purpose I/Os (GPIO)
Bits 9:8 MODE4[1:0]: Port Px4 IO type configuration
Bits 7:6 MODE3[1:0]: Port Px3 IO type configuration
Bits 5:4 MODE2[1:0]: Port Px2 IO type configuration
Bits 3:2 MODE1[1:0]: Port Px1 IO type configuration
Bits 1:0 MODE0[1:0]: Port Px0 IO type configuration
10.4.2 GPIOx output type register (GPIOx_OTYPER) (x = A to B)
Address offset: Block A: 0x0004
Address offset: Block B: 0x0404
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
OT15 OT14 OT13 OT12
rw rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 OT[15:0]: Port Px[15:0] output type configuration
10.4.3 GPIOx output speed register (GPIOx_OSPEEDR) (x = A to B)
Address offset: Block A: 0x0008
Address offset: Block B: 0x0408
Reset value: Block A: 0x0C00 0000
Reset value: Block B: 0x0000 00C0
31 30 29
OSPEED15[1:0] OSPEED14[1:0] OSPEED13[1:0]
rw rw rw
15 14 13
OSPEED7[1:0] OSPEED6[1:0]
rw rw rw
402/1454
These bits are written by software to configure the I/O mode.
00: Input mode
01: General purpose output mode
10: Alternate function mode
11: Analog mode (reset state)
27 26 25
Res. Res. Res.
11 10 9
OT11 OT10 OT9
rw rw rw
These bits are written by software to configure the I/O output type.
0: Output push-pull (reset state)
1: Output open-drain
28 27 26 25
OSPEED12[1:0]
rw rw rw rw
12 11 10 9
OSPEED5[1:0] OSPEED4[1:0]
rw rw rw rw
24 23 22
Res. Res. Res. Res.
8 7 6
OT8 OT7 OT6 OT5
rw rw rw
24 23 22
OSPEED11[1:0]
rw rw rw
8 7 6
OSPEED3[1:0]
rw rw rw
RM0453 Rev 2
21 20 19 18
Res. Res. Res.
5 4 3 2
OT4 OT3 OT2
rw rw rw rw
21 20 19 18
OSPEED10[1:0] OSPEED9[1:0]
rw rw rw rw
5 4 3
OSPEED2[1:0] OSPEED1[1:0]
rw rw rw rw
RM0453
17 16
Res. Res.
1 0
OT1 OT0
rw rw
17 16
OSPEED8[1:0]
rw rw
2 1 0
OSPEED0[1:0]
rw rw