ST STM32WL55JC Reference Manual page 687

RM0453
23.7.2 AES status register (AES_SR)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:4 Reserved, must be kept at reset value.
Bit 3 BUSY: Busy
This flag indicates whether AES is idle or busy during GCM payload encryption phase:
0: Idle
1: Busy
When the flag indicates "idle", the current GCM encryption processing may be suspended to
process a higher-priority message. In other chaining modes, or in GCM phases other than payload
encryption, the flag must be ignored for the suspend process.
Bit 2 WRERR: Write error
This flag indicates the detection of an unexpected write operation to the AES_DINR register (during
computation or data output phase):
0: Not detected
1: Detected
The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR
register.
Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR
register.
The flag setting has no impact on the AES operation. Unexpected write is ignored.
Bit 1 RDERR: Read error flag
This flag indicates the detection of an unexpected read operation from the AES_DOUTR register
(during computation or data input phase):
0: Not detected
1: Detected
The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR
register.
Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR
register.
The flag setting has no impact on the AES operation. Unexpected read returns zero.
Bit 0 CCF: Computation completed flag
This flag indicates whether the computation is completed:
0: Not completed
1: Completed
The flag is set by hardware upon the completion of the computation. It is cleared by software, upon
setting the CCFC bit of the AES_CR register.
Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the AES_CR
register.
The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1.
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
RM0453 Rev 2
AES hardware accelerator (AES)
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
Res. Res. Res. Res.
19 18 17
Res. Res. Res. Res.
3 2 1
BUSY WRERR RDERR CCF
r r r
687/1454
16
0
r
695