ST STM32WL55JC Reference Manual page 213

RM0453
5.10.22 Sub-GHz radio receiver gain control register (SUBGHZ_RXGAINCR)
Address offset: 0x08AC
Reset value: 0x94
7 6
rw rw
Bits 7:2 SENSI_ADJUST[5:0]: Sensitivity Floor of AGC
Bits 1:0 PMODE[1:0]: Receiver power mode selection between normal mode and power saving mode
5.10.23 Sub-GHz radio PA over current protection register
(SUBGHZ_PAOCPR)
Address offset: 0x08E7
Reset value: 0x18
7 6
Res. Res.
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:0 OCP[5:0]: Power amplifier over current protection level
5.10.24 Sub-GHz radio HSE32 OSC_IN capacitor trim register
(SUBGHZ_HSEINTRIMR)
Address offset: 0x0911
Reset value: 0x12
This register is retained in Sleep mode, but lost in Deep-Sleep mode.
7 6
Res. Res.
5
SENSI_ADJUST[5:0]
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This bitfield must be kept at 0x25.
00: power saving mode (reduced sensitivity)
01: boost mode level1 active (improves sensitivity at detriment of power consumption)
10: boost mode level2 active (improves a set further sensitivity at detriment of power
consumption)
Others: boost mode (best receiver sensitivity)
5
rw
0x18: maximum 60 mA current for LP PA mode
0x38: maximum 140mA current for HP PA mode.
Others: reserved
5
rw
4 3
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4 3
OCP[5:0]
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4 3
TRIM[5:0]
rw rw
RM0453 Rev 2
Sub-GHz radio (SUBGHZ)
2 1
PMODE[1:0]
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2 1
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2 1
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0
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0
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0
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