ST STM32WL55JC Reference Manual page 868

General-purpose timer (TIM2)
Bit 4 DIR: Direction
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
Bit 3 OPM: One-pulse mode
Bit 2 URS: Update request source
Bit 1 UDIS: Update disable
Bit 0 CEN: Counter enable
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
CEN is cleared automatically in one-pulse mode, when an update event occurs.
26.4.2 TIM2 control register 2 (TIM2_CR2)
Address offset: 0x04
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
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0: Counter used as upcounter
1: Counter used as downcounter
mode.
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
0: Counter disabled
1: Counter enabled
previously set by software. However trigger mode can set the CEN bit automatically by
hardware.
12 11 10 9
Res. Res. Res.
8 7 6
Res. TI1S MMS[2:0]
rw rw
RM0453 Rev 2
5 4 3 2
CCDS Res.
rw rw rw
RM0453
1 0
Res. Res.