Figure 42. Ipcc Half-Duplex - Receive Procedure State Diagram - ST STM32WL55JC Reference Manual

RM0453
GPIOx_BSRR and GPIOx_BRR registers allow atomic read/modify accesses to any of the
GPIOx_ODR registers. In this way, there is no risk of an IRQ occurring between the read
and the modify access.
Figure 43
bit.
Table 70
Analog
To on-chip
peripheral
Alternate function input
Read
Write
Read/write
From on-chip
Alternate function output
peripheral
and Figure 44 show the basic structure of a standard and a 5V-tolerant I/O port
gives the possible port bit configurations.
Figure 43. Basic structure of a standard I/O port bit
Input driver
Output driver
on/off
trigger
V
DDIOx
P-MOS
Output
control
N-MOS
V
SS
Push-pull,
open-drain or
disabled
RM0453 Rev 2
General-purpose I/Os (GPIO)
V
DDIOx
V
DDIOx
Protection
on/off
diode
Pull
up
I/O pin
on/off
Protection
Pull
down
diode
V
SS
V
SS
Analog
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