Table 188. Tim16/Tim17 Register Map And Reset Values - ST STM32WL55JC Reference Manual

Low-power timer (LPTIM)
28.3 LPTIM implementation
Table 189
features is implemented in LPTIM1. LPTIM2 and LPTIM3 support a smaller set of features,
but is otherwise identical to LPTIM1.
LPTIM modes/features
Encoder mode
External input clock
Wakeup from Stop
1. X = supported.
2. Wakeup supported from Stop 0, Stop 1 and Stop 2 modes.
3. Wakeup supported from Stop 0 and Stop 1 modes.
28.4 LPTIM functional description
28.4.1 LPTIM block diagram
LPTIM
APB clock
domain
LPTIM
register
interface
APB clock
LPTIM IRQ
interrupt interface
lptim_ker_ck
Wakeup
1. lptim_out is the internal LPTIM output signal that can be connected to internal peripherals.
a. LPTIM2/LPTIM3 has only the input channel 1, no input channel 2.
946/1454
describes LPTIM implementation on STM32WL5x devices. The full set of
Table 189. STM32WL5x LPTIM features
(1)
Figure 261. Low-power timer block diagram
Up/down
Encoder
Glitch
filter
1
CLKMUX
0
Edge detector
Edge detector
CNTSTRT/
16-bit ARR
SNGSTRT
Mux trigger
1
1 0
16-bit counter
Count mode
Prescaler
16-bit compare
RM0453 Rev 2
LPTIM1 LPTIM2
X -
X X
(2) (3)
(a)
Kernel clock domain
Glitch
filter
Glitch
filter
LPTIM_RCR
Repetition
counter
RM0453
LPTIM3
-
X
(3)
lptim_in2
LPTIM_IN2
lptim_in1
LPTIM_IN1
lptim_ext_trigx
LPTIM_ETR
LPTIM_OUT
(1)
lptim_out
MSv47413V3