Pwr Control Register 5 (Pwr_Cr5) - ST STM32WL55JC Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Power control (PWR)
6.6.23
PWR register map
Offset
Register
PWR_CR1
0x000
Reset value
PWR_CR2
0x004
Reset value
PWR_CR3
0x008
Reset value
PWR_CR4
0x00C
Reset value
PWR_SR1
0x010
Reset value
PWR_SR2
0x014
Reset value
PWR_SCR
0x018
Reset value
PWR_CR5
0x01C
Reset value
PWR_PUCRA
0x020
Reset value
PWR_PDCRA
0x024
Reset value
PWR_PUCRB
0x028
Reset value
274/1454
Table 56. PWR register map and reset values
RM0453 Rev 2
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RM0453
LPMS
[2:0]
0
0
0
0
0 0
PLS [2:0]
0
0
0
0 0
0
0 0
0
0 0
0
0 0
0
0
0
0
0
0 0
0
0 0
0
0
0
0
0
0 0
0
0
0
0
0
0 0
0
0
0
0
0
0 0

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