Table 115. Sample And Refresh Timings - ST STM32WL55JC Reference Manual

Digital-to-analog converter (DAC)
V
1
V
d
V
2
dac_hold
_ck
DAC
Like in Normal mode, the Sample and hold mode has different configurations.
To enable the output buffer, MODE1[2:0] bits in DAC_MCR register must be set to:
•
100: DAC is connected to the external pin
•
101: DAC is connected to external pin and to on chip peripherals
To disabled the output buffer, MODE1[2:0] bits in DAC_MCR register must be set to:
•
110: DAC is connected to external pin and to on chip peripherals
•
111: DAC is connected to on chip peripherals
When MODE1[2:0] bits are equal to 111, an internal capacitor, C
output of the DAC core and then drive it to on-chip peripherals.
All Sample and hold phases are interruptible, and any change in DAC_DHR1 immediately
triggers a new sample phase.
1
MODE [2:0] Mode
0 0 0
0 0 1
Normal mode
0 1 0
0 1 1
602/1454
Figure 93. DAC Sample and hold mode phase diagram
Sampling phase
ON
Table 116. Channel output modes summary
Buffer
Connected to external pin
Enabled
Connected to external pin and to on chip-peripherals (such as
comparators)
Connected to external pin
Disabled
Connected to on chip peripherals (such as comparators)
Hold phase
Refresh
phase
ON
Output connections
RM0453 Rev 2
RM0453
t
Sampling phase
t
ON
MSv45340V3
holds the voltage
,
Lint