Pwr Status Register 1 (Pwr_Sr1) - ST STM32WL55JC Reference Manual

Power control (PWR)
Bit 10 APC: Apply pull-up and pull-down configuration for CPU2
Bit 9 Reserved, must be kept at reset value.
Bit 8 EWPVD: PVD and wakeup for CPU2 enable (when sub-GHz radio is in active state)
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 EWUP3: Enable wakeup pin WKUP3 for CPU2
Bit 1 EWUP2: wakeup pin WKUP2 for CPU2 enable
Bit 0 EWUP1: wakeup pin WKUP1 for CPU2 enable
6.6.19 PWR extended status and status clear register (PWR_EXTSCR)
Access: three additional APB cycles are needed to write this register versus a standard APB
write.
Address offset: 0x088
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
C2DS C1DS
r r r
270/1454
When this bit for CPU2, and the PWR_CR3.APC bit for CPU1, are set, the I/O pull-up and
pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are
applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not
applied to the I/Os.
This bit is set and reset by software.
When this bit is set, PVD is enabled while the sub-GHz radio is active and triggers an
interrupt and wakeup from Standby event to CPU2, when the voltage level drops below the
PVD threshold level.
0: PVD not enabled by the sub-GHz radio active state
1: PVD enabled while the sub-GHz radio is active
When this bit is set, the external wakeup pin WKUP3 is enabled and triggers an interrupt and
wakeup from Stop, Standby or Shutdown event to CPU2 when a rising or a falling edge
occurs. The active edge is configured via the WP3 bit in the
(PWR_CR4).
When this bit is set, the external wakeup pin WKUP2 is enabled and triggers an interrupt and
wakeup from Stop, Standby or Shutdown event to CPU2 when a rising or a falling edge
occurs . The active edge is configured via the WP2 bit in the
(PWR_CR4).
When this bit is set, the external wakeup pin WKUP1 is enabled and triggers an interrupt and
wakeup from Stop, Standby or Shutdown event to CPU2 when a rising or a falling edge
occurs. The active edge is configured via the WP1 bit in the
(PWR_CR4).
28 27 26 25
Res. Res. Res.
12 11 10 9
C2SBF
r r r r
24 23 22
Res. Res. Res.
8 7 6
C1SBF Res. Res.
r
RM0453 Rev 2
PWR control register 4
PWR control register 4
PWR control register 4
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. Res. Res. Res.
RM0453
17 16
Res. Res.
1 0
w w