ST STM32WL55JC Reference Manual page 587

RM0453
18.12.13 ADC Analog Watchdog 2 Configuration register (ADC_AWD2CR)
Address offset: 0xA0
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
AWD2 AWD2 AWD2 AWD2
CH15 CH14 CH13 CH12
rw rw rw
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:0 AWD2CH[17:0]: Analog watchdog channel selection
These bits are set and cleared by software. They enable and select the input channels to be guarded
by analog watchdog 2 (AWD2).
0: ADC analog channel-x is not monitored by AWD2
1: ADC analog channel-x is monitored by AWD2
Note: The channels selected through ADC_AWD2CR must be also configured into the
ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is
allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is
ongoing).
18.12.14 ADC Analog Watchdog 3 Configuration register (ADC_AWD3CR)
Address offset: 0xA4
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
AWD3 AWD3 AWD3 AWD3
CH15 CH14 CH13 CH12
rw rw rw
Bits 31:18 Reserved, must be kept at reset value.
Bits 17:0 AWD3CH[17:0]: Analog watchdog channel selection
These bits are set and cleared by software. They enable and select the input channels to be guarded
by analog watchdog 3 (AWD3).
0: ADC analog channel-x is not monitored by AWD3
1: ADC analog channel-x is monitored by AWD3
Note: The channels selected through ADC_AWD3CR must be also configured into the
ADC_CHSELR registers. Refer to SQ8[3:0] for a definition of channel selection. The software is
allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).
28 27 26 25
Res. Res. Res.
12 11 10 9
AWD2 AWD2 AWD2
CH11 CH10 CH9
rw rw rw rw
28 27 26 25
Res. Res. Res.
12 11 10 9
AWD3 AWD3 AWD3
CH11 CH10 CH9
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
AWD2 AWD2 AWD2 AWD2
CH8 CH7 CH6
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
AWD3 AWD3 AWD3 AWD3
CH8 CH7 CH6
rw rw rw
RM0453 Rev 2
Analog-to-digital converter (ADC)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
AWD2 AWD2 AWD2
CH5 CH4 CH3 CH2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
AWD3 AWD3 AWD3
CH5 CH4 CH3 CH2
rw rw rw rw
17 16
AWD2 AWD2
CH17 CH16
rw rw
1 0
AWD2 AWD2
CH1 CH0
rw rw
17 16
AWD3 AWD3
CH17 CH16
rw rw
1 0
AWD3 AWD3
CH1 CH0
rw rw
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