ST STM32WL55JC Reference Manual page 516

Extended interrupts and event controller (EXTI)
Bits 31:23 Reserved, must be kept at reset value.
Bit 22 PIF22: pending bit on event input 22
Bit 21 PIF21: pending bit on event input 21
Bits 20:17 Reserved, must be kept at reset value.
Bit 16 PIF16: pending bit on event input 16
Bit 15 PIF15: pending bit on event input 15
Bit 14 PIF14: pending bit on event input 14
Bit 13 PIF13: pending bit on event input 13
Bit 12 PIF12: pending bit on event input 12
Bit 11 PIF11: pending bit on event input 11
Bit 10 PIF10: pending bit on event input 10
Bit 9 PIF9: pending bit on event input 9
Bit 8 PIF8: pending bit on event input 8
Bit 7 PIF7: pending bit on event input 7
Bit 6 PIF6: pending bit on event input 6
Bit 5 PIF5: pending bit on event input 5
Bit 4 PIF4: pending bit on event input 4
Bit 3 PIF3: pending bit on event input 3
Bit 2 PIF2: pending bit on event input 2
Bit 1 PIF1: pending bit on event input 1
Bit 0 PIF0: pending bit on event input 0
16.6.5 EXTI rising trigger selection register (EXTI_RTSR2)
Address offset: 0x020
Reset value: 0x0000 0000
Contains only register bits for configurable events.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. RT45 Res.
rw
516/1454
These bits are set when the selected edge event or an EXTI_SWIER software trigger arrives
on the configurable event line. This bit is cleared by writing 1 to it.
0: No trigger request occurred.
1: Trigger request occurred.
27 26 25
Res. Res. Res.
11 10 9
Res. Res. RT41
rw
24 23 22
Res. Res. Res. Res.
8 7 6
RT40 Res. Res. Res.
rw
RM0453 Rev 2
21 20 19 18
Res. Res. Res.
5 4 3 2
Res. Res. RT34
rw
RM0453
17 16
Res. Res.
1 0
Res. Res.