ST STM32WL55JC Reference Manual page 502

Nested vectored interrupt controller (NVIC)
Type of
priority
59 66 Settable DMA2_CH6
60 67 Settable DMA2_CH7
61 68 Settable DMAMUX1_OVR
1. IMRx[n] refer to the pre-mask bit[n] in SYSCFG_IMRx register.
2. EXTI[n] refer to the input event number [n] of the EXTI.
Type of
priority
- - -
- -3 Fixed
-14 -2 Fixed
-13 -1 Fixed
- - -
-5 0 Settable
- - -
-2 1 Settable
-1 2 Settable
0 3 Settable
1 4 Settable PVD, PVM[3]
RTC_STAMP,
2 5 Settable
RTC_ALARM,
RTC_SSRU,
RTC_WKUP
3 6 Settable
4 7 Settable
5 8 Settable
502/1454
Table 89. CPU1 vector table (continued)
Acronym
DMA2 channel 6 non-secure interrupt
DMA2 channel 7 non-secure interrupt
DMAMUX1 overrun interrupt
Table 90. CPU2 vector table
Acronym
- Reserved
Reset Reset
Non maskable interrupt HSE CSS, Flash ECC and SRAM2
NMI
parity
HardFault All classes of fault
- Reserved
SVCall System service can via SWI instruction
- Reserved
PendSV Pendable request for system service
Systick System tick timer
TZIC_ILA Security Interrupt controller illegal access interrupt
PVD through EXTI[16] (C2IMR2[20])
PVM[3] through EXTI[34] (C2IMR2[18])
TAMP, TAMP tamper
RTC timestamp
LSE_CSS, LSECSS interrupt (C2IMR1[0])
RTC alarms A and B interrupt (C2IMR1[1])
RTC SSR underflow interrupt (C2IMR1[2])
RTC wakeup interrupt (C2IMR1[3])
RCC, RCC global interrupt (C2IMR1[5])
FLASH, Flash memory global interrupt and Flash memory ECC
single error interrupt (C2IMR1[6])
C1SEV CPU1 SEV through EXTI[41]
EXTI[1:0] EXTI line 1:0 interrupt through EXTI[1:0] (C2IMR1[17:16])
EXTI[3:2] EXTI line 3:2 interrupt through EXTI[3:2] (C2IMR1[19:18])
Description
(1)(2)
Description
RM0453 Rev 2
(1)(2)
RM0453
Address
0x0000 012C
0x0000 0130
0x0000 0134
Address
0x0000 0000
0x0000 0004
0x0000 0008
0x0000 000C
0x0000 0010
0x0000 0028
0x0000 002C
0x0000 0030
0x0000 0034
0x0000 0038
0x0000 003C
0x0000 0040
0x0000 0044
0x0000 0048
0x0000 004C
0x0000 0050
0x0000 0054