ST STM32WL55JC Reference Manual page 506

Extended interrupts and event controller (EXTI)
The masking block provides the event input distribution to the different wakeup, interrupt
and event outputs, and the masking of these.
AHB interface
hclk
Wakeup
Direct event(x) or
configurable event(y)
Interrupt
Direct event(x)
1) it_exti_per(y) only available for configurable events (y)
Pin name I/O
AHB interface I/O
hclk I
Configurable
I
event(y)
Direct event(x) I
it_exti_per (y) O
cn_evt_exti O
cn_evt_rst I
sys_wakeup O
cn_wakeup O
Pin name
cn_fclk
cn_evt_in
cn_event
cn_evt_rst
506/1454
Figure 54. EXTI block diagram
Registers
Masking
Events
Event
trigger
EXTI
Table 91. EXTI pin overview
EXTI register bus interface
AHB bus clock and EXTI system clock
Asynchronous wakeup events from peripherals which do not have an associated interrupt
and flag in the peripheral
Synchronous and asynchronous wakeup events from peripherals which have an
associated interrupt and flag in the peripheral
Interrupts to the CPU associated with the configurable event (y)
High-level sensitive event output for the CPUn, synchronous to hclk
Asynchronous reset input to clear cn_evt_exti
Asynchronous system wakeup request to PWR for ck_sys and hclk
Wakeup request to PWR for the CPUn, synchronous to hclk
Table 92. EVG pin overview
I/O
I CPUn free running clock
I High-level sensitive events input from EXTI, asynchronous to the CPUn clock
O Event pulse, synchronous to the CPUn clock
O Event reset signal, synchronous to the CPUn clock
sys_wakeup
c1_wakeup
c2_wakeup
(1)
it_exti_per(y)
c1_evt_exti
c1_evt_rst
EVG
c2_evt_exti
c2_evt_rst
Description
Description
RM0453 Rev 2
c1_event
Pulse
rxev
nvic(x)
c1_fclk
nvic(y)
c2_event
Pulse
rxev
nvic(x)
c2_fclk
EVG
nvic(y)
RM0453
PWR
CPU1
CPU2
MSv60758V1