ST STM32WL55JC Reference Manual page 140

Embedded Flash memory (FLASH)
access is ignored and an illegal access event is generated. Unprivileged read access is still
allowed.
31 30 29
Res. Res. Res.
rs
15 14 13
Res. Res. Res. Res.
Bit 31 PCROP_RDP: PCROP area preserved when RDP level decreased
Bits 30:8 Reserved, must be kept at reset value.
Bits 7:0 PCROP1A_END[7:0]: PCROP1A area end offset
4.10.11 FLASH WRP area A address register (FLASH_WRP1AR)
Address offset: 0x02C
Reset value: 0xFF80 FFFF
Default reset value from ST production is given as.0b1111 1111 1XXX XXXX 1111 1111
1XXX XXXX, the option bits are loaded with user values from the Flash memory at reset
release.
Access: no wait state when no Flash memory operation is ongoing. Word, half-word and
byte access.
This register can only be written by the CPU1 in RDP level 0 or RDP level 1.
When the system is secure (ESE = 1), this register is further more protected by the
PRIVMODE. When privilege protection is enabled in PRIVMODE, this register provides
write access privilege and can only be written by a privileged access. Unprivileged write
access is ignored and an illegal access event is generated. Unprivileged read access is still
allowed.
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
140/1454
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
This bit is set only. It is reset after a full mass erase due to a change of RDP from level 1 to
level 0.
0: PCROP area not erased when the RDP level is decreased from level 1 to level 0
1: PCROP area erased when the RDP level is decreased from level 1 to level 0 (full mass
erase)
PCROP1A_END contains the last 1-Kbyte page of the PCROP1A area.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
Res.
rw rw
24 23 22
Res. Res.
rw
8 7 6
Res. Res.
rw
RM0453 Rev 2
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
PCROP1A_END[7:0]
rw rw rw rw
21 20 19 18
WRP1A_END[6:0]
rw rw rw rw
5 4 3 2
WRP1A_STRT[6:0]
rw rw rw rw
RM0453
17 16
Res. Res.
1 0
rw rw
17 16
rw rw
1 0
rw rw