ST STM32WL55JC Reference Manual page 492

DMA request multiplexer (DMAMUX)
Bit 9 EGE: Event generation enable
0: Event generation disabled
1: Event generation enabled
Bit 8 SOIE: Synchronization overrun interrupt enable
0: Interrupt disabled
1: Interrupt enabled
Bits 7:0 DMAREQ_ID[7:0]: DMA request identification
Selects the input DMA request. See the DMAMUX table about assignments of multiplexer
inputs to resources.
14.6.2 DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR)
Address offset: 0x080
Reset value: 0x0000 0000
This register must be accessed at bit level by a non-secure or secure read, according to the
secure mode of the considered DMAMUX request line multiplexer channel x, depending on
the secure mode bit of the connected DMA controller channel y, and considering that the
DMAMUX x channel output is connected to the y channel of the DMA (refer to the DMAMUX
mapping implementation section).
31 30 29
Res. Res. Res.
15 14 13
Res. Res. SOF13 SOF12
r
Bits 31:14 Reserved, must be kept at reset value.
Bits 13:0 SOF[13:0]: Synchronization overrun event flag
The flag is set when a synchronization event occurs on a DMA request line multiplexer
channel x, while the DMA request counter value is lower than NBREQ.
The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CFR
DMAMUX_CCFR register.
14.6.3 DMAMUX request line multiplexer interrupt channel clear flag register
(DMAMUX_CCFR)
Address offset: 0x084
Reset value: 0x0000 0000
This register must be written at bit level by a non-secure or secure write, according to the
secure mode of the considered DMAMUX request line multiplexer channel x, depending on
the secure control bit of the connected DMA controller channel y, and considering that the
DMAMUX x channel output is connected to the y channel of the DMA (refer to the
DMAMXUX mapping implementation section).
This register must be written at bit level by an unprivileged or privileged write, according to
the privileged mode of the considered DMAMUX request line multiplexer channel x,
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28 27 26 25
Res. Res. Res. Res.
12 11 10 9
SOF11 SOF10 SOF9
r r r
24 23 22
Res. Res. Res.
8 7 6
SOF8 SOF7 SOF6
r r r r
RM0453 Rev 2
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
SOF5 SOF4 SOF3 SOF2
r r r r
RM0453
17 16
Res. Res.
1 0
SOF1 SOF0
r r