Table 98. Crc Internal Input/Output Signals; Figure 57. Crc Calculation Unit Block Diagram - ST STM32WL55JC Reference Manual

RM0453
17.4 CRC registers
The CRC_DR register can be accessed by words, right-aligned half-words and right-aligned
bytes. For the other registers only 32-bit accesses are allowed.
17.4.1 CRC data register (CRC_DR)
Address offset: 0x00
Reset value: 0xFFFF FFFF
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 DR[31:0]: Data register bits
This register is used to write new data to the CRC calculator.
It holds the previous CRC calculation result when it is read.
If the data size is less than 32 bits, the least significant bits are used to write/read the correct
value.
17.4.2 CRC independent data register (CRC_IDR)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
Bits 31:0 IDR[31:0]: General-purpose 32-bit data register bits
These bits can be used as a temporary storage location for four bytes.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR
register
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
27 26 25
rw rw rw
11 10 9
rw rw rw
Cyclic redundancy check calculation unit (CRC)
24 23 22
DR[31:16]
rw rw rw
8 7 6
DR[15:0]
rw rw rw
24 23 22
IDR[31:16]
rw rw rw
8 7 6
IDR[15:0]
rw rw rw
RM0453 Rev 2
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
17 16
rw rw
1 0
rw rw
17 16
rw rw
1 0
rw rw
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