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RM0453
31.5.3
WWDG status register (WWDG_SR)
Address offset: 0x008
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 EWIF: Early wakeup interrupt flag
31.5.4
WWDG register map
The following table gives the WWDG register map and reset values.
Offset
Register
WWDG_CR
0x000
Reset value
WWDG_CFR
0x004
Reset value
WWDG_SR
0x008
Reset value
Refer to
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared
by software by writing '0'. Writing '1' has no effect. This bit is also set if the interrupt is not
enabled.
Table 206. WWDG register map and reset values
Section 2.6 on page 70
System window watchdog (WWDG)
24
23
22
Res.
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
Res.
for the register boundary addresses.
RM0453 Rev 2
21
20
19
18
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
0
1
WDGTB
[2:0]
0
0
0
0
1
17
16
Res.
Res.
1
0
Res.
EWIF
rc_w0
T[6:0]
1
1
1
1
1
1
W[6:0]
1
1
1
1
1
1
0
989/1454
989
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