ST STM32WL55JC Reference Manual page 470

Direct memory access controller (DMA)
Setting any of the DSEC or SSEC bits must be performed by a secure write access to this
register.
Except SECM and PRIV control bits, any other register field is non-readable by a
non-secure software if the SECM bit is set, and non-readable by an unprivileged software if
the PRIV bit is set.
The register fields/bits PRIV, DSEC, SSEC, SECM,MEM2MEM, PL[1:0], MSIZE[1:0],
PSIZE[1:0], MINC, PINC, and DIR are read-only when EN = 1.
The states of MEM2MEM and CIRC bits must not be both high at the same time.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
MEM2
Res. PL[1:0]
MEM
rw rw rw
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 PRIV: privileged mode
This bit can only be set and cleared by a privileged software.
0: disabled
1: enabled
This bit must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 19 DSEC: security of the DMA transfer to the destination
This bit can only be read, set or cleared by a secure software. It must be a privileged software
if the channel is in privileged mode.
This bit is cleared by hardware when the securely written data bit 17 is cleared (on a secure
reconfiguration of the channel as non -secure).
A non-secure read to this secure configuration bit returns 0.
A non-secure write of 1 to this secure configuration bit has no impact on the register setting
and an illegal access pulse is asserted.
Destination (peripheral or memory) of the DMA transfer is defined by the direction DIR
configuration bit.
0: non-secure DMA transfer to the destination
1: secure DMA transfer to the destination
This bit must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
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27 26 25 24
Res. Res. Res. Res.
11 10 9 8
MSIZE[1:0] PSIZE[1:0]
rw rw rw rw
RM0453 Rev 2
23 22 21 20
Res. Res. Res. PRIV
rw
7 6 5
MINC PINC CIRC DIR
rw rw rw rw
19 18 17
DSEC SSEC SECM
rw rw rw
4 3 2 1
TEIE HTIE TCIE
rw rw rw
RM0453
16
Res.
0
EN
rw