ST STM32WL55JC Reference Manual page 545

RM0453
18.3.13 Timings
The elapsed time between the start of a conversion and the end of conversion is the sum of
the configured sampling time plus the successive approximation time depending on data
resolution:
t
CONV
t
CONV
ADC state
Analog
channel
Internal S/H
ADSTART
EOSMP
EOC
ADC_DR
depends on SMP[2:0]
(1) t
SMPL
depends on RES[2:0]
(2) t
SAR
ADSTART
ADC state
ADC_DR
1. EXTEN
2. Trigger latency (refer to datasheet for more details)
3. ADC_DR register write latency (refer to datasheet for more details)
= t + t = [1.5
SMPL SAR |min
= t + t = 42.9 ns
SMPL SAR
Figure 64. Analog to digital conversion time
RDY SAMPLING CH(N)
CH(N)
Sample AIN(N+1)
t (1)
SMPL
set
by SW
Figure 65. ADC conversion timings
(1)
(2)
t
LATENCY
Ready S0
=
00 or EXTEN ≠ 00
+ 12.5 ] x t
|12bit ADC_CLK
+ 357.1 ns = 0.400 µs
|min |12bit
CONVERTING CH(N)
Hold AIN(N)
cleared by SW
set by HW
DATA N-1
Conversion 0 S1 Conversion 1
(3)
W
LATENCY
Data 0
RM0453 Rev 2
Analog-to-digital converter (ADC)
(for f
|min ADC_CLK
t (2)
SAR
set
by HW
S2 Conversion 2 S3
(3)
W W
LATENCY LATENCY
Data 1
= 35 MHz)
SAMPLING CH(N+1)
CH(N+1)
Sample AIN(N+1)
cleared
by SW
DATA N
MS30336V1
Conversion 3
(3)
Data 2
MSv33174V1
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