Flash Cpu2 Control Register (Flash_C2Cr) - ST STM32WL55JC Reference Manual

Embedded Flash memory (FLASH)
Bit 1 PER: page erase
Bit 0 PG: programming
4.10.19 FLASH secure Flash start address register (FLASH_SFR)
Address offset: 0x080
Reset value: 0xFFFF EFFF
Default reset value from ST production is given as 0bX111 1111 XXXX XXXX 111X 1111
XXXX XXXX, the option bits are loaded with user values from the Flash memory at power-
on reset release.
When the system is secure (ESE = 1), this register provides write access security and can
only be written by the CPU2. A write access from the CPU1 is ignored and an illegal access
event is generated. On any read access the register value is returned.
When the system is secure (ESE = 1), this register is further more protected by the
PRIVMODE. When privilege protection is enabled in PRIVMODE, this register provides
write access privilege and can only be written by a privileged access. Unprivileged write
access from is ignored and an illegal access event is generated. Unprivileged read access
is still allowed.
This register, except for the DDS bit, is further write protected by HDPADIS, when
HDPAD = 0. The write protected bits can only be written when HDPADIS = 0. When
HDPADIS = 1, write access is ignored. Read access returns register data.
Written values are only taken into account after OBL.
There are no read restrictions.
31 30 29
Res. Res.
rw
15 14 13
Res. Res. Res.
Bit 31 SUBGHSPISD: sub-GHz radio SPI security disable
Bits 30:24 Reserved, must be kept at reset value.
148/1454
0: page erase disabled
1: page erase enabled
0: Flash programming disabled
1: Flash programming enabled
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
DDS Res. Res. Res.
rw
When FSD = 1, the sub-GHz radio SPI security is disabled whatever the value of this
SUBGHSPISD bit.
This bit is write protected when HDPAD = 0 and HDPADIS = 1.
0 (and FSD = 0): sub-GHz radio SPI security enabled
1 (and FSD = 0): sub-GHz radio SPI security disabled
24 23 22
Res. HDPAD
rw rw
8 7 6
Res. FSD
rw rw
RM0453 Rev 2
21 20 19 18
HDPSA[6:0]
rw rw rw rw
5 4 3 2
SFSA[6:0]
rw rw rw rw
RM0453
17 16
rw rw
1 0
rw rw