ST STM32WL55JC Reference Manual page 642

True random number generator (RNG)
Interrupt acronym
RNG
The user can enable or disable the above interrupt sources individually by changing the
mask bits or the general interrupt control bit IE in the RNG_CR register. The status of the
individual interrupt sources can be read from the RNG_SR register.
Note: Interrupts are generated only when RNG is enabled.
22.5 RNG processing time
In NIST compliant configuration, the time between two sets of four 32-bit data is either:
•
412 AHB cycles if f
•
256 RNG cycles f
With f
threshold
Note: When CLKDIV is different from zero, f
22.6 RNG entropy source validation
22.6.1 Introduction
In order to assess the amount of entropy available from the RNG, STMicroelectronics has
tested the peripheral using German BSI AIS-31 statistical tests (T0 to T8), and NIST
SP800-90B test suite. The results can be provided on demand or the customer can
reproduce the tests.
22.6.2 Validation conditions
STMicroelectronics has tested the RNG true random number generator in the following
conditions:
•
RNG clock rng_clk= 48 MHz
•
RNG configurations described in
certified NIST SP800-90B.
RNG
NISTC RNG_CONFIG1
Config
bit
A 0
B 1
642/1454
Table 130. RNG interrupt requests
Interrupt event Event flag
Data ready flag
Seed error flag
Clock error flag
< f
AHB threshold
≥ f
AHB threshold
= 1.6 x f , e.g. 77 MHz if f
RNG
Table 131. RNG configurations
RNG_CR bits
CLKDIV
[5:0] [3:0]
0x0F 0x0
0x18 0x0
Enable control bit
DRDY IE
SEIS IE
CEIS IE
(conditioning stage is limiting), or
(noise source stage is limiting).
= 48 MHz.
RNG
must take into account the internal divider ratio.
RNG
Table 131. Note that only configuration A can be
RNG_CONFIG2 RNG_CONFIG3
[2:0]
0x0
0x0
RM0453 Rev 2
Interrupt clear method
None (automatic)
Write 0 to SEIS or write
CONDRST to 1 then to 0
Write 0 to CEIS
Nb
loop
CED
(N)
[3:0] bit
0xD 0 2
0x0 0 2
RM0453
RNG_HTCR
(1)
register
0x0000
A2B3