ST STM32WL55JC Reference Manual page 584

Analog-to-digital converter (ADC)
18.12.10 ADC channel selection register [alternate] (ADC_CHSELR)
Address offset: 0x28
Reset value: 0x0000 0000
The same register can be used in two different modes:
– Each ADC_CHSELR bit enables an input (CHSELRMOD = 0 in ADC_CFGR1). Refer to
the current previous section.
– ADC_CHSELR is able to sequence up to 8 channels (CHSELRMOD = 1 in
ADC_CFGR1). Refer to this section.
CHSELRMOD = 1 in ADC_CFGR1:
31 30 29
SQ8[3:0]
rw rw rw
15 14 13
SQ4[3:0]
rw rw rw
Bits 31:28 SQ8[3:0]: 8th conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates the end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
0000: CH0
0001: CH1
...
1100: CH12
1101: CH13
1110: CH14
1111: No channel selected (End of sequence)
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 27:24 SQ7[3:0]: 7th conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 23:20 SQ6[3:0]: 6th conversion of the sequence
These bits are programmed by software with the channel number (0...14) assigned to the 8th
conversion of the sequence. 0b1111 indicates end of the sequence.
When 0b1111 (end of sequence) is programmed to the lower sequence channels, these bits are
ignored.
Refer to SQ8[3:0] for a definition of channel selection.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
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28 27 26 25
SQ7[3:0]
rw rw rw rw
12 11 10 9
SQ3[3:0]
rw rw rw rw
24 23 22
SQ6[3:0]
rw rw rw
8 7 6
SQ2[3:0]
rw rw rw
RM0453 Rev 2
21 20 19 18
SQ5[3:0]
rw rw rw rw
5 4 3 2
SQ1[3:0]
rw rw rw rw
RM0453
17 16
rw rw
1 0
rw rw