ST STM32WL55JC Reference Manual page 941

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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RM0453
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bits 1:0 TI1_RMP[1:0]: Timer 17 input 1 connection
This bit is set and cleared by software.
00: TIM17 TI1 is connected to GPIO
01: TIM17 TI1 is connected to MSI
10: TIM17 TI1 is connected to HSE/32
11: TIM17 TI1 is connected to MCO
27.4.21
TIM17 alternate function register 1 (TIM17_AF1)
Address offset: 0x60
Reset value: 0x0000 0001
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 BKCMP2P: BRK COMP2 input polarity
This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP
polarity bit.
0: COMP2 input is active low
1: COMP2 input is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 10 BKCMP1P: BRK COMP1 input polarity
This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP
polarity bit.
0: COMP1 input is active low
1: COMP1 input is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
BKCM
BKCM
BKINP
P2P
P1P
rw
rw
rw
in TIMx_BDTR register).
in TIMx_BDTR register).
General-purpose timers (TIM16/TIM17)
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0453 Rev 2
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
BKCM
Res.
Res.
Res.
P2E
rw
17
16
Res.
Res.
1
0
TI1_RMP[1:0]
rw
rw
17
16
Res.
Res.
1
0
BKCM
BKINE
P1E
rw
rw
941/1454
944

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