ST STM32WL55JC Reference Manual page 152

Embedded Flash memory (FLASH)
4.10.21 FLASH register map
Offset Register
FLASH_ACR
0x000
Reset value
FLASH_ACR2
0x004
Reset value
FLASH_KEYR
0x008
Reset value 0
FLASH_
OPTKEYR
0x00C
Reset value 0
FLASH_SR
0x010
Reset value
FLASH_CR
0x014
Reset value 1
FLASH_ECCR
0x018
Reset value 0
FLASH_OPTR
0x020
Reset value 0
FLASH_
PCROP1ASR
0x024
Reset value
FLASH_
PCROP1AER
0x028
Reset value 1
FLASH_
WRP1AR
0x02C
Reset value
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Table 25. Flash interface register map and reset values
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 0 0 0 0
CPUID
[2:0]
0 0 0 0 0
0 1 1 1 1 1
0 0
KEYR[31:0]
0 0 0 0 0 0 0 0 0
OPTKEY[31:0]
0 0 0 0 0 0 0 0 0
X X X 0 0
0 0 0
0 0 0 0
1 1 1 1 1
WRP1A_END[6:0]
0 0 0 0 0 0 0
RM0453 Rev 2
0 0 1 1 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
PNB[6:0]
0 0 0 0 0
ADDR_ECC[16:0]
0 0 0 0 0 0 0 0 0
BOR_LEV
[2:0]
1 1 0 0 0 0 1 0 1
PCROP1A_STRT[7:0]
1 1 1
PCROP1A_END[7:0]
0 0 0
WRP1A_STRT[6:0]
1 1
RM0453
LATENCY
[2:0]
0 0 0
X 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0
0 0 0 0 0
0 0 0 0 0
RDP[7:0]
0 1 0 1 0
1 1 1 1 1
0 0 0 0 0
1 1 1 1 1