ST STM32WL55JC Reference Manual page 68

Memory and bus architecture
This example show only a secure and privileged protected memory map. The security and
unprivileged parameters can freely be programmed in any order as detailed below:
•
When HDPSA > SFSA> unprivileged watermark > unprivileged write watermark, the
areas appear in the following order:
–
–
–
–
–
•
unprivileged write watermark >= unprivileged watermark, the areas appear in the
following order:
–
–
Memory access protection overview
The secure area of the memories have exclusively read, write, execute access only from the
secure CPU2 and secure DMA channels. CPU1 and non-secure DMA channels have no
execute, read, nor write access to these areas.
The non-secure area of the memories grants full read, write, execute access to CPU1 and
all DMA channels. CPU2 has only read and write access to the non-secure areas. CPU2 is
prevented from executing from non-secure areas.
Access rules from the different bus masters and secure, non-secure, privileged and
unprivileged access types to the different memory areas is given in the table below.
SoC level memory area
Hide protection secure
privileged
Secure privileged
Secure privileged
Unprivileged execution
Secure unprivileged
Non-secure privileged
Non-secure unprivileged
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Secure privileged hide protection area at the top
Secure privileged area
Non-secure privileged area
Non-secure unprivileged read only area
Non-secure unprivileged area starting from the memory base address.
privileged area at the top
Unprivileged area starting from the memory base address (no unprivileged read
only area in this case)
Table 3. Memory security and privilege access
no
access
(1)
ex, rd,
wr
ex, rd,
wr
rd, wr rd, wr
no
access
(2)
no
access
no
(2)
(3)
ex, rd
access
(2)
ex, rd,
wr
no
access
ex, rd,
(2)(4)
wr
ex, rd,
rd, wr
wr
RM0453 Rev 2
(rd, wr)
no
(1)
access
(2)
no
access
(2)
rd
rd, wr
rd, wr
no
access
(2)(4)
rd, wr
rd, wr
RM0453
no
access
(2)
rd, wr