Gtzc Tzsc Register Map; Table 9. Gtzc Tzsc Register Map And Reset Values - ST STM32WL55JC Reference Manual

RM0453
Bit 7 DMA1IE: Illegal access event interrupt enable bit for DMA1
Bit 6 FLASHIFIE: Illegal access event interrupt enable bit for FLASH interface
Bit 5 PWRIE: Illegal access event interrupt enable bit for PWR
Bit 4 SUBGHZSPIIE: Illegal access event interrupt enable bit for sub-GHz SPI
Bit 3 RNGIE: Illegal access event interrupt enable bit for RNG
Bit 2 AESIE: Illegal access event interrupt enable bit for AES
Bit 1 TZSCIE: Illegal access event interrupt enable bit for GTZC TZSC
Bit 0 TZICIE: Illegal access event interrupt enable bit for GTZC TZIC
3.6.2 GTZC TZIC status register 1 (GTZC_TZIC_MISR1)
Address offset: 0x010
Reset value: 0x0000 0000
This register can only be access by a secure privileged access for read and write. A non
secure or unprivileged access is ignored and return zero data and an illegal access event is
generated.
Note: When the system is non-secure (ESE = 0) this register cannot be written and reads zero.
31 30 29
Res. Res. Res. Res.
15 14 13
SRAM2
Res. Res. PKAMF
r
Bits 31:14 Reserved, must be kept at reset value.
0: Disabled (masked)
1: Enabled (unmasked)
0: Disabled (masked)
1: Enabled (unmasked)
0: Disabled (masked)
1: Enabled (unmasked)
0: Disabled (masked)
1: Enabled (unmasked)
0: Disabled (masked)
1: Enabled (unmasked)
0: Disabled (masked)
1: Enabled (unmasked)
0: Disabled (masked)
1: Enabled (unmasked)
0: Disabled (masked)
1: Enabled (unmasked)
28 27 26 25
Res. Res. Res.
12 11 10 9
SRAM1 FLASH DMAM
MF MF MF UX1MF
r r r r
24 23 22
Res. Res. Res.
8 7 6
DMA2 DMA1 FLASHI PWR
MF MF FMF
r r r
RM0453 Rev 2
Global security controller (GTZC)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
SUBG
RNG
HZSPI AESMF
MF MF
MF
r r r r
17 16
Res. Res.
1 0
TZSC TZIC
MF MF
r r
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