ST STM32WL55JC Reference Manual page 312

Reset and clock control (RCC)
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 GPIOHRST: IO port H reset
Bits 6:3 Reserved, must be kept at reset value.
Bit 2 GPIOCRST: IO port C reset
Bit 1 GPIOBRST: IO port B reset
Bit 0 GPIOARST: IO port A reset
7.4.10 RCC AHB3 peripheral reset register (RCC_AHB3RSTR)
Address offset: 0x030
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29
Res. Res. Res.
15 14 13
Res. Res. Res.
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 FLASHRST: Flash interface reset
Bits 24:21 Reserved, must be kept at reset value.
Bit 20 IPCCRST: IPCC interface reset
312/1454
This bit is set and cleared by software.
0: No effect
1: IO port H reset
This bit is set and cleared by software.
0: No effect
1: IO port C reset
This bit is set and cleared by software.
0: No effect
1: IO port B reset
This bit is set and cleared by software.
0: No effect
1: IO port A reset
28 27 26 25
FLASH
Res. Res. Res.
RST
rw
12 11 10 9
Res. Res. Res. Res.
This bit can only be set when the Flash memory is in power down. It is set and cleared by
software.
0: No effect
1: Flash memory interface reset
This bit is set and cleared by software.
0: No effect
1: IPCC reset
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0453 Rev 2
21 20 19 18
IPCC HSEM RNG
Res.
RST RST RST
rw rw rw
5 4 3 2
Res. Res. Res. Res.
RM0453
17 16
AES PKA
RST RST
rw rw
1 0
Res. Res.