Gtzc Tzsc Unprivileged Watermark 2 Register (Gtzc_Tzsc_Mpcwm2_Upwmr) - ST STM32WL55JC Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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RM0453
3.5.8
GTZC TZSC register map
2
Register
Offset
GTZC_TZSC_CR
0x000
Reset value
0x004
to
Reserved
0x00C
GTZC_TZSC_
SECCFGR1
0x010
Reset value
0x014
to
Reserved
0x01C
GTZC_TZSC_
PRIVCFGR1
0x020
Reset value
0x024
to
Reserved
0x12C
GTZC_TZSC_
MPCWM1_UPWMR
0x130
Reset value
GTZC_TZSC_
MPCWM1_
0x134
UPWWMR
Reset value
GTZC_TZSC_
MPCWM2_UPWMR
0x138
Reset value
0x13C
Reserved
GTZC_TZSC_
MPCWM3_UPWMR
0x140
Reset value
Refer to
Table 9. GTZC TZSC register map and reset values
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Section 2.6
for the register boundary addresses.
Reserved
Reserved
Reserved
LGTH[11:0]
1
1
1
1
1
1
1
1
LGTH[11:0]
1
1
1
1
1
1
1
1
LGTH[11:0]
1
1
1
1
1
1
1
1
Reserved
LGTH[11:0]
1
1
1
1
1
1
1
1
RM0453 Rev 2
Global security controller (GTZC)
0
0
0
0
0
0
0
0
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