Gtzc Tzsc Unprivileged Writable Watermark 1 Register (Gtzc_Tzsc_Mpcwm1_Upwwmr) - ST STM32WL55JC Reference Manual

Global security controller (GTZC)
3.5.7 GTZC TZSC unprivileged watermark 3 register
(GTZC_TZSC_MPCWM3_UPWMR)
Address offset: 0x140
Reset value: 0x0FFF 0000
Privileged write access only.
This register can be written only by secure privileged transaction, when the corresponding
Flash user option BRSD is configured as secure. If non-secure, this register can be written
by secure privileged and non-secure privileged transaction.
Read access is authorized for any type of transaction, secure/non-secure,
privileged/unprivileged.
When TZSC configuration is locked in GTZC_TZSC_CR.LCK, this register cannot be
modified.
Note: When the system is non-secure (ESE = 0), this register can be written and read, however
bits have no function.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 LGTH[11:0]: Define the length of SRAM2 unprivileged area (in 1-Kbyte resolution, starting
from the SRAM2 base address)
Note: This register has only effect when security is enabled (ESE = 1). When security is
Note: 0x800 and greater are truncated to 0x800
Bits 15:0 Reserved, must be kept at reset value.
90/1454
28 27 26 25
rw rw rw
12 11 10 9
Res. Res. Res.
disabled, the memory is completely unprivileged, whatever the value.
0x000: No unprivileged area, privileged 0x0000 to 0x7FFF
0x001: Unprivileged 0x0000 to 0x03FF, privileged 0x0400 to 0x7FFF
0x002: Unprivileged 0x0000 to 0x07FF, privileged 0x0800 to 0x7FFF
0x003: Unprivileged 0x0000 to 0x0BFF, privileged 0x0C00 to 0x7FFF
.....
0x020 and greater: Unprivileged 0x0000 to 0x7FFF, no privileged area
24 23 22
LGTH[11:0]
rw rw rw
8 7 6
Res. Res. Res.
RM0453 Rev 2
21 20 19 18
rw rw rw rw
5 4 3 2
Res. Res. Res. Res.
RM0453
17 16
rw rw
1 0
Res. Res.