Table 187. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature; (Tim16/17) - ST STM32WL55JC Reference Manual

RM0453
27.4.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17)
Address offset: 0x44
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. BKBID
15 14 13
MOE AOE BKP BKE
rw rw rw
Note: As the BKBID, BKDSRM, AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] bits may be write-
locked depending on the LOCK configuration, it may be necessary to configure all of them
during the first write access to the TIMx_BDTR register.
Bits 31:29 Reserved, must be kept at reset value.
Bit 28 BKBID: Break Bidirectional
0: Break input BRK in input mode
1: Break input BRK in bidirectional mode
In the bidirectional mode (BKBID bit set to 1), the break input is configured both in input
mode and in open drain output mode. Any active break event asserts a low logic level on the
Break input to indicate an internal break event to external devices.
Note: This bit cannot be modified as long as LOCK level 1 has been programmed (LOCK bits
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bit 27 Reserved, must be kept at reset value.
Bit 26 BKDSRM: Break Disarm
0: Break input BRK is armed
1: Break input BRK is disarmed
This bit is cleared by hardware when no break source is active.
The BKDSRM bit must be set by software to release the bidirectional output control (open-
drain output in Hi-Z state) and then be polled it until it is reset by hardware, indicating that the
fault condition has disappeared.
Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.
Bits 25:20 Reserved, must be kept at reset value.
Bits 19:16 Reserved, must be kept at reset value.
Bit 15 MOE: Main output enable
This bit is cleared asynchronously by hardware as soon as the break input is active. It is set
by software or automatically depending on the AOE bit. It is acting only on the channels
which are configured in output.
0: OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit.
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in
TIMx_CCER register)
See OC/OCN enable description for more details
enable register (TIMx_CCER)(x = 16 to 17) on page
28 27 26 25
BK
Res. Res.
DSRM
rw rw
12 11 10 9
OSSR OSSI LOCK[1:0]
rw rw rw rw
in TIMx_BDTR register).
General-purpose timers (TIM16/TIM17)
24 23 22
Res. Res. Res.
8 7 6
rw rw rw
(Section 27.4.8: TIMx capture/compare
RM0453 Rev 2
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
DTG[7:0]
rw rw rw rw
930).
17 16
Res. Res.
1 0
rw rw
935/1454
944