Figure 232. Master/Slave Connection Example With 1 Channel Only Timers - ST STM32WL55JC Reference Manual

General-purpose timer (TIM2)
TIM1-CEN=CNT_EN
TIM1-CNT_INIT
TIM2-CNT_INIT
TIM2-write CNT
Using one timer to start another timer
In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to
Figure 231
non-zero) on the divided internal clock as soon as the update event is generated by Timer 1.
When Timer 2 receives the trigger signal its CEN bit is automatically set and the counter
counts until we write '0 to the CEN bit in the TIM2_CR1 register. Both counter clock
frequencies are divided by 3 by the prescaler compared to CK_INT (f
1. Configure TIM1 master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIM1_CR2 register).
2. Configure the TIM1 period (TIM1_ARR registers).
3. Configure TIM2 to get the input trigger from TIM1 (TS=00000 in the TIM2_SMCR
register).
4. Configure TIM2 in trigger mode (SMS=110 in TIM2_SMCR register).
5. Start TIM1 by writing '1 in the CEN bit (TIM1_CR1 register).
TIM2-CEN=CNT_EN
864/1454
Figure 234. Gating TIM2 with Enable of TIM1
CK_INT
TIM1-CNT
75
TIM2-CNT
AB
TIM2-TIF
for connections. Timer 2 starts counting from its current value (which can be
Figure 235. Triggering TIM2 with update of TIM1
CK_INT
TIM1-UEV
TIM1-CNT
FD
TIM2-CNT
TIM2-TIF
00
00 E7
Write TIF = 0
FE FF
45
Write TIF = 0
RM0453 Rev 2
01 02
E8 E9
CK_CNT
00 01 02
46 47 48
RM0453
MS32696V1
= f /3).
CK_INT
MS32697V1