ST STM32WL55JC Reference Manual page 310

Reset and clock control (RCC)
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 LSECSSC: LSE CSS flag clear
Bit 8 CSSC: HSE32 CSS flag clear
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 PLLRDYC: PLL ready interrupt clear
Bit 4 HSERDYC: HSE32 ready interrupt clear
Bit 3 HSIRDYC: HSI16 ready interrupt clear
Bit 2 MSIRDYC: MSI ready interrupt clear
Bit 1 LSERDYC: LSE ready interrupt clear
Bit 0 LSIRDYC: LSI ready interrupt clear
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This bit is set by software to clear the LSECSSF flag.
0: No effect
1: LSECSSF flag cleared
This bit is set by software to clear the HSE32 CSSF flag.
0: No effect
1: HSE32 CSSF flag cleared
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: PLLRDYF flag cleared
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: HSERDYF flag cleared
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: HSIRDYF flag cleared
This bit is set by software to clear the MSIRDYF flag.
0: No effect
1: MSIRDYF flag cleared
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF flag cleared
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF flag cleared
RM0453 Rev 2
RM0453