Flash Ipcc Mailbox Data Buffer Address Register; (Flash_Ipccbr); Flash Ipcc Mailbox Data Buffer Address Register (Flash_Ipccbr) - ST STM32WL55JC Reference Manual

RM0453
Bits 31:20 Reserved, must be kept at reset value.
Bit 19 PESD: program/erase operation suspended
Bit 18 CFGBSY: program or erase configuration busy
Bit 17 Reserved, must be kept at reset value.
Bit 16 BSY: Busy
Bit 15 Reserved, must be kept at reset value.
Bit 14 RDERR: PCROP read error
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 FASTERR: fast programming error
Bit 8 MISSERR: fast programming data miss error
Bit 7 PGSERR: programming sequence error
Bit 6 SIZERR: size error
This bit is set and reset by hardware. This bit is set when at least one PES bit in
FLASH_ACR or FLASH_C2ACR is set.
This bit is cleared when both PES in FLASH_ACR and FLASH_C2ACR are cleared.
When set, new program or erase operations are not started.
This bit is set and reset by hardware (set when first word is sent and reset when program
operation completes or is interrupt by an error).
When set, the program and erase settings in PG, and PNB in FLASH_C2CR are used (busy)
and may not be changed. A Flash program or erase operation is ongoing.
When reset, program and erase settings in PG and PNB in FLASH_C2CR may be modified.
This bit indicates that a Flash operation requested in FLASH_C2CR is in progress. This bit is
set on the beginning of a Flash operation and reset when the operation finishes or when an
error occurs.
This bit is set by hardware when an address to be read through the D-bus belongs to a read
protected area of the Flash memory (PCROP protection). An interrupt is generated if
RDERRIE is set in FLASH_CR.
This bit is cleared by writing 1.
This bit is set by hardware when a fast programming sequence (activated by FSTPG) is
interrupted due to an error (alignment, size, write protection or data miss). The
corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at the same
time.
This bit is cleared by writing 1.
In fast programming mode, 32 double-words (256 bytes) must be sent to the Flash memory
successively, and the new data must be sent to the Flash memory logic control before the
current data is fully programmed. This bit is set by hardware when the new data is not
present in time.
This bit is cleared by writing 1.
This bit is set by hardware when a write access to the Flash memory is performed by the
code while PG or FSTPG have not been set previously. This bit is also set by hardware when
PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous
programming error.
This bit is cleared by writing 1.
This bit is set by hardware when the size of the access is a byte or half-word during a
program or a fast program sequence. Only double-word programming is allowed
(consequently: word access).
This bit is cleared by writing 1.
RM0453 Rev 2
Embedded Flash memory (FLASH)
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